This paper describes the methodology used to design and evaluate the strength and reliability of the thermal interface between the chip and heat sink (coverplate) in a TBGA first level package. TBGA is a new technology that is part of the new generation of organic ball grid array chip carriers that are quickly gaining popularity for packaging various microprocessors and memory in portables, desktops, mid-range and high-end mainframes. The package consists of a Kapton or Upilex dielectric layer with one signal plane and one ground plane on either side, as shown in Figure 1. The chip is attached to the package with the signal side ‘down’, that is, facing the card. This leaves the backside of the chip available for coverplate (flat copper heat sink) attach. This direct access to the chip allows for a very effective thermal path from the chip directly to the heat sink, resulting in outstanding thermal performance. It is therefore essential to ensure that the interface between the chip and the heat sink remains intact through the end of the assembly processes for the package, including second-level attach to the board and rework. The interface must also remain intact through the life of the product. It is also necessary to ensure that the interface survives all of the necessary qualification stresses including accelerated thermal cycling, thermal age and deep thermal cycling, to name a few. First the results of a numerical analysis are presented showing the impact of surface de-lamination upon the thermal performance of the package. The model used is a full three-dimensional conjugate model accounting for conduction and radiation effects in the package, as well as the natural convection flow in the surrounding air. The results confirm that delamination of the interface degrades the thermal performance of the package. The model and test results also indicate that, due to the robustness of the package, voids or incomplete coverage of the chip with the thermal adhesive results in a relatively small degradation of the thermal performance of the package, provided total de-lamination of the chip or coverplate does not occur. The methodology used in evaluating different design options, such as adhesive material and heat sink surface treatment, is then described in detail. The primary method used for evaluating interfacial strength is a modified fracture toughness test (MFTT). This is the best measure of resistance to crack propagation. In conjunction with the MFTT, a sonographic technique was used to evaluate the integrity of the interface as a function of stress. Finally, a laser moiré tool is employed to evaluate the strains in the package due to thermal stress. The moiré results are shown for an intact package as well as for a completely de-laminated package, showing the differences in the mechanical response of the package due to delamination.

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