This work presents an easy to use approach to quickly estimate the device temperatures and thermal stresses in a generic high power module. A low order model was developed in MATLAB using a combination of numerical-analytical approach and a 3D nodal resistor network to calculate device temperatures and thermal stresses. The model assumes a heat flux generated at the top of each device which is dissipated through the packaging structure and removed by convection. The temperature distribution is used to calculate thermal stresses throughout the package. This method eliminates computer aided drawings (CAD) in favor of numerical parameters that can be easily and quickly varied over a wide range. The resistor network solves quickly in MATLAB, enabling fast, iterative thermal analyses and design through parametric studies of the chip dimensions, number of chips, chip layout, material types, cooling solutions, etc. The model is adaptable to any number of devices and board layers. The MATLAB model reduced the computational time by 97% compared to an equivalent SOLIDWORKS finite element analysis (FEA) model and that does not include the time required to generate the CAD model and verify mesh convergence and mesh independence. Temperatures from the network model were within 5°C and stresses were within 30% of the values obtained from the FEA model. The ability to quickly assess the thermal and stress effects of a wide variety of power module design parameters during the initial design process, without the complexity of a full FEA analysis, with reasonable results can significantly improve the final module.
- Electronic and Photonic Packaging Division
Power Packaging Thermal and Stress Model for Quick Parametric Analyses
- Views Icon Views
- Share Icon Share
- Search Site
Boteler, LM, & Miner, SM. "Power Packaging Thermal and Stress Model for Quick Parametric Analyses." Proceedings of the ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2017 Conference on Information Storage and Processing Systems. ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. San Francisco, California, USA. August 29–September 1, 2017. V001T04A012. ASME. https://doi.org/10.1115/IPACK2017-74130
Download citation file: