Enhancements to thermal performance of FC-PBGA packages due to underfill thermal conductivity, controlled collapse chip connection (C4) pitch, package to printed wiring board (PWB) interconnection through thermal balls, a heat spreader on the backside of the die, and an overmolded die with and without a heat spreader have been studied by solving a conjugate heat transfer problem. These enhancements have been investigated under natural and forced convection conditions for freestream velocities up to 2 m/s. The following ranges of parameters have been covered in this study: substrate size: 25–35 mm, die size: 6.19×7.81 mm (48 mm2 area) and 9.13×12.95 mm (118 mm2 area), underfill thermal conductivity: 0.6–3.0 W/(m K), C4 pitch: 250 μm and below, no thermal balls to 9×9 array of thermal balls on 1.27 mm square pitch, and with copper heat spreader on the back of a bare and an overmolded die. Based on our previous work, predictions in this study are expected to be within ±10% of measured data. The conclusions of the study are: (i) Thermal conductivity of the underfill in the range 0.6 to 10 W/(m K) has negligible effect on thermal performance of FC-PBGA packages investigated here. (ii) Thermal resistances decrease 12–15% as C4 pitch decreases below 250 μm. This enhancement is smaller with increase in die area. (iii) Thermal balls connected to the PTHs in the PWB decrease thermal resistance of the package by 10–15% with 9×9 array of thermal balls and PTHs compared to no thermal balls. The effect of die size on this enhancement is more noticeable on junction to board thermal resistance, than the other two package thermal metrics. (iv) Heat spreader on the back of the die decreases junction-to-ambient thermal resistance, by 6% in natural convection and by 25% in forced convection. (v) An overmolded die with a heat spreader provides better a thermal enhancement than a heat spreader on a bare die for freestream velocities up to about 1 m/s. Beyond 1 m/s, a heat spreader on bare die has better thermal performance.
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December 2004
Research Papers
Evaluation of Thermal Enhancements to Flip-Chip-Plastic Ball Grid Array Packages
K. Ramakrishna, Fellow ASME,,
K. Ramakrishna, Fellow ASME,
Interconnect Reliability, CMOS Platform Device Development, Technology Solutions Organization, Freescale Semiconductor, Inc., 3501 Ed Bluestein Boulevard, TX11/K10, Austin, TX 78721
11
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T.-Y. Tom Lee, Mem. ASME,
T.-Y. Tom Lee, Mem. ASME,
Final Manufacturing Technology Center, Technology and Manufacturing Organization, Freescale Semiconductor, Inc., 2100 E. Elliot Road, AZ34/EL725, Tempe, AZ 78524
Search for other works by this author on:
K. Ramakrishna, Fellow ASME,
11
Interconnect Reliability, CMOS Platform Device Development, Technology Solutions Organization, Freescale Semiconductor, Inc., 3501 Ed Bluestein Boulevard, TX11/K10, Austin, TX 78721
T.-Y. Tom Lee, Mem. ASME,
Final Manufacturing Technology Center, Technology and Manufacturing Organization, Freescale Semiconductor, Inc., 2100 E. Elliot Road, AZ34/EL725, Tempe, AZ 78524
Paper presented at the IMECE 2003 in Washington, D.C. November 15–21, 2003 at Symposium Honoring Richard C. Chu, Paper No. IMECE2003-42397. Manuscript received April 26, 2004; revision received June 23, 2004. Review conducted by: B. Sammakia.
J. Electron. Packag. Dec 2004, 126(4): 449-456 (8 pages)
Published Online: January 24, 2005
Article history
Received:
April 26, 2004
Revised:
June 23, 2004
Online:
January 24, 2005
Citation
Ramakrishna, K., and Lee, T. T. (January 24, 2005). "Evaluation of Thermal Enhancements to Flip-Chip-Plastic Ball Grid Array Packages ." ASME. J. Electron. Packag. December 2004; 126(4): 449–456. https://doi.org/10.1115/1.1827260
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