Due to low cost and good electrical performance, wafer-level chip scale packaging (WLCSP) has gained more attention in both industry and academia. However, because the coefficient of thermal expansion (CTE) mismatches between silicon and organic printed circuit board (PCB), WLCSP technology still faces reliability challenges, such as the solder joint fragile life issue. In this paper, a new WLCSP design (WLCSP-PN) is proposed, based on the structure of WLCSP with Cu posts (WLCSP-P), to release the stress on the solder joints. In the new design, there is a space between the Cu post and the polymer which permits NiSn coating on the post sidewall. The overcoating enhances the solder–post interface where cracks were initiated and enlarges the intermetallic compounds (IMC) joint area to enhance the adhesion strength. Design of experiment (DOE) with the Taguchi method is adopted to obtain the sensitivity information of design parameters of the new design by the three-dimensional (3D) finite element model (FEM), leading to the optimized configuration. The finite element analysis results demonstrate that compared to WLCSP-P, the proposed WLCSP-PN reduces the package displacement, equivalent stress, and plastic strain energy density and thus improves the fatigue life of solder joints.
Skip Nav Destination
Article navigation
March 2018
Research-Article
Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging
Lei Shi,
Lei Shi
State Key Laboratory of ASIC and System,
School of Microelectronics,
Fudan University,
Shanghai 200433, China
School of Microelectronics,
Fudan University,
Shanghai 200433, China
Search for other works by this author on:
Lin Chen,
Lin Chen
State Key Laboratory of ASIC and System,
School of Microelectronics,
Fudan University,
Shanghai 200433, China
School of Microelectronics,
Fudan University,
Shanghai 200433, China
Search for other works by this author on:
David Wei Zhang,
David Wei Zhang
State Key Laboratory of ASIC and System,
School of Microelectronics,
Fudan University,
Shanghai 200433, China
e-mail: dwzhang@fudan.edu.cn
School of Microelectronics,
Fudan University,
Shanghai 200433, China
e-mail: dwzhang@fudan.edu.cn
Search for other works by this author on:
Evan Liu,
Evan Liu
Tongfu Microelectronics Co., LTD,
Nantong 226006, Jiangsu, China
Nantong 226006, Jiangsu, China
Search for other works by this author on:
Qiang Liu,
Qiang Liu
Tongfu Microelectronics Co., LTD,
Nantong 226006, Jiangsu, China;
Nantong 226006, Jiangsu, China;
Search for other works by this author on:
Ching-I Chen
Ching-I Chen
Mechanical Engineering,
Chung Hua University,
Hsinchu 30012, Taiwan
Chung Hua University,
Hsinchu 30012, Taiwan
Search for other works by this author on:
Lei Shi
State Key Laboratory of ASIC and System,
School of Microelectronics,
Fudan University,
Shanghai 200433, China
School of Microelectronics,
Fudan University,
Shanghai 200433, China
Lin Chen
State Key Laboratory of ASIC and System,
School of Microelectronics,
Fudan University,
Shanghai 200433, China
School of Microelectronics,
Fudan University,
Shanghai 200433, China
David Wei Zhang
State Key Laboratory of ASIC and System,
School of Microelectronics,
Fudan University,
Shanghai 200433, China
e-mail: dwzhang@fudan.edu.cn
School of Microelectronics,
Fudan University,
Shanghai 200433, China
e-mail: dwzhang@fudan.edu.cn
Evan Liu
Tongfu Microelectronics Co., LTD,
Nantong 226006, Jiangsu, China
Nantong 226006, Jiangsu, China
Qiang Liu
Tongfu Microelectronics Co., LTD,
Nantong 226006, Jiangsu, China;
Nantong 226006, Jiangsu, China;
Ching-I Chen
Mechanical Engineering,
Chung Hua University,
Hsinchu 30012, Taiwan
Chung Hua University,
Hsinchu 30012, Taiwan
Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received March 23, 2017; final manuscript received October 6, 2017; published online March 2, 2018. Assoc. Editor: Kaushik Mysore.
J. Electron. Packag. Mar 2018, 140(1): 011002 (9 pages)
Published Online: March 2, 2018
Article history
Received:
March 23, 2017
Revised:
October 6, 2017
Citation
Shi, L., Chen, L., Zhang, D. W., Liu, E., Liu, Q., and Chen, C. (March 2, 2018). "Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging." ASME. J. Electron. Packag. March 2018; 140(1): 011002. https://doi.org/10.1115/1.4038245
Download citation file:
Get Email Alerts
Cited By
Anand Model Constants of Sn-Ag-Cu Solders: What Do They Actually Mean?
J. Electron. Packag
Enhancing Mechanical Reliability of Silver-Sintered Joints With Copper Nanowires in High-Power Electronic Devices
J. Electron. Packag (December 2024)
Special Issue on InterPACK2023
J. Electron. Packag (December 2024)
Related Articles
Effect of Intermetallic Compounds on the Thermomechanical Fatigue Life of Three-Dimensional Integrated Circuit Package Microsolder Bumps: Finite Element Analysis and Study
J. Electron. Packag (December,2015)
Reliability Modeling of Lead-Free Solder Joints in Wafer-Level Chip Scale Packages
J. Electron. Packag (March,2010)
Thermal Cycling Study of Quilt Packaging
J. Electron. Packag (June,2015)
Fatigue Properties and Microstructure of SnAgCu Bi-Based Solder Joint
J. Electron. Packag (March,2021)
Related Proceedings Papers
Related Chapters
Analysis of Components in VIII-2
Guidebook for the Design of ASME Section VIII Pressure Vessels, Third Edition
Thermotriples
Hot Air Rises and Heat Sinks: Everything You Know about Cooling Electronics Is Wrong
A Dependable Answer
Hot Air Rises and Heat Sinks: Everything You Know about Cooling Electronics Is Wrong