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Keywords: Chip Scale Package
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Journal Articles

Direct Concentration Approach of Moisture Diffusion and Whole-Field Vapor Pressure Modeling for Reflow Process—Part II: Application to 3D Ultrathin Stacked-Die Chip Scale Packages

B. Xie, X. J. Fan, X. Q. Shi, H. Ding
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Research Papers
J. Electron. Packag. September 2009, 131(3): 031011.
https://doi.org/10.1115/1.3144154
Published Online: July 31, 2009
... Process: Part I–Theory and Numerical Implementation,” ASME J. Electron. Packag., 131, p. 031010 ) is applied to 3D ultrathin stacked-die chip scale packages to investigate wafer-level die-attach film cohesive failures during the reflow process. Oversaturation, which refers to the film that absorbs more...
View Article titled, Direct Concentration Approach of Moisture Diffusion and Whole-Field Vapor Pressure Modeling for Reflow Process—Part II: Application to 3D Ultrathin Stacked-Die <span class="search-highlight">Chip</span> <span class="search-highlight">Scale</span> <span class="search-highlight">Packages</span>
Open the PDF for Direct Concentration Approach of Moisture Diffusion and Whole-Field Vapor Pressure Modeling for Reflow Process—Part II: Application to 3D Ultrathin Stacked-Die <span class="search-highlight">Chip</span> <span class="search-highlight">Scale</span> <span class="search-highlight">Packages</span> in another window
Topics: Diffusion (Physics), Vapor pressure, Failure, Modeling
Journal Articles

Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging

Y. T. Lin, Graduate Assistant, C. T. Peng, Graduate Assistant, K. N. Chiang, Associate Professor
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Papers On Reliability
J. Electron. Packag. September 2002, 124(3): 234–239.
https://doi.org/10.1115/1.1481368
Published Online: July 26, 2002
...Y. T. Lin, Graduate Assistant; C. T. Peng, Graduate Assistant; K. N. Chiang, Associate Professor The demands for electronic packages with lower profile, lighter weight, and higher input/output (I/O) density have led to rapid expansion in flip chip, chip scale package (CSP) and wafer level packaging...
View Article titled, Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging
Open the PDF for Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging in another window
Topics: Copper, Event history analysis, Finite element methods, Flip-chip, Packaging, Reliability, Semiconductor wafers, Solders, Wire, Finite element analysis