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Keywords: Chip Scale Package
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Journal Articles
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Research Papers
J. Electron. Packag. September 2009, 131(3): 031011.
Published Online: July 31, 2009
... Process: Part I–Theory and Numerical Implementation,” ASME J. Electron. Packag., 131, p. 031010 ) is applied to 3D ultrathin stacked-die chip scale packages to investigate wafer-level die-attach film cohesive failures during the reflow process. Oversaturation, which refers to the film that absorbs more...
Journal Articles
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Papers On Reliability
J. Electron. Packag. September 2002, 124(3): 234–239.
Published Online: July 26, 2002
...Y. T. Lin, Graduate Assistant; C. T. Peng, Graduate Assistant; K. N. Chiang, Associate Professor The demands for electronic packages with lower profile, lighter weight, and higher input/output (I/O) density have led to rapid expansion in flip chip, chip scale package (CSP) and wafer level packaging...