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Keywords: Wafer Level Packaging
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Journal Articles
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. September 2018, 140(3): 031004.
Paper No: EP-17-1127
Published Online: May 11, 2018
... OURNAL OF E LECTRONIC P ACKAGING . Manuscript received December 11, 2017; final manuscript received February 14, 2018; published online May 11, 2018. Assoc. Editor: Yi-Shao Lai. 11 12 2017 14 02 2018 3D packaging Wafer level packaging Wafer scale three-dimensional...
Journal Articles
Publisher: ASME
Article Type: Guest Editorial
J. Electron. Packag. June 2018, 140(2): 020301.
Paper No: EP-18-1012
Published Online: May 9, 2018
... SOC Wafer level packaging The United States Government retains, and by accepting the article for publication, the publisher acknowledges that the United States Government retains, a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this work...
Journal Articles
Publisher: ASME
Article Type: Guest Editorial
J. Electron. Packag. June 2017, 139(2): 020301.
Paper No: EP-17-1032
Published Online: June 12, 2017
...Justin A. Weibel; S. Ravi Annapragada 22 03 2017 31 03 2017 3D packaging Backplanes Chip stacking Failure analysis Flexible circuits Nanotechnolgy Reliability Solder Thermal analysis Underfill Wafer level packaging ASME's International Mechanical Engineering...
Journal Articles
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. December 2016, 138(4): 041001.
Paper No: EP-14-1082
Published Online: August 10, 2016
... September 29, 2014; final manuscript received July 14, 2016; published online August 10, 2016. Assoc. Editor: Toru Ikeda. 29 09 2014 14 07 2016 3D packaging Area array COB CSP FR-4 Wafer level packaging Mechanical failures of hand-held devices lose their effective...
Journal Articles
Publisher: ASME
Article Type: Review Articles
J. Electron. Packag. September 2016, 138(3): 030802.
Paper No: EP-16-1052
Published Online: July 25, 2016
..., 2016; published online July 25, 2016. Assoc. Editor: Eric Wong. 06 04 2016 22 06 2016 3D packaging High density interconnects Underfill Wafer level packaging In this paper, a flip chip is defined [ 1 – 4 ] as a chip attached to the pads of a substrate or another chip...
Journal Articles
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. December 2015, 137(4): 041005.
Paper No: EP-14-1064
Published Online: October 12, 2015
.... The most widely used methods are based on the standards set by Joint Electron Devices Engineering Council (JEDEC) [ 1 ]. Flip chip Wafer level packaging 30 06 2014 16 09 2015 Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the J OURNAL...
Journal Articles
Journal Articles
Publisher: ASME
Article Type: Review Articles
J. Electron. Packag. March 2015, 137(1): 010801.
Paper No: EP-14-1069
Published Online: November 14, 2014
... back to the evaporator as shown in Fig. 1 [ 1 ]. 3D packaging Flexible circuits MEMS Microsystems Nanotechnolgy Thermal analysis Wafer level packaging 04 08 2014 10 10 2014 Contributed by the Electronic and Photonic Packaging Division of ASME for publication...
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