Skip Nav Destination
Close Modal
Update search
Filter
- Title
- Author
- Author Affiliations
- Full Text
- Abstract
- Keyword
- DOI
- ISBN
- ISBN-10
- ISSN
- EISSN
- Issue
- Journal Volume Number
- References
- Conference Volume Title
- Paper No
Filter
- Title
- Author
- Author Affiliations
- Full Text
- Abstract
- Keyword
- DOI
- ISBN
- ISBN-10
- ISSN
- EISSN
- Issue
- Journal Volume Number
- References
- Conference Volume Title
- Paper No
Filter
- Title
- Author
- Author Affiliations
- Full Text
- Abstract
- Keyword
- DOI
- ISBN
- ISBN-10
- ISSN
- EISSN
- Issue
- Journal Volume Number
- References
- Conference Volume Title
- Paper No
Filter
- Title
- Author
- Author Affiliations
- Full Text
- Abstract
- Keyword
- DOI
- ISBN
- ISBN-10
- ISSN
- EISSN
- Issue
- Journal Volume Number
- References
- Conference Volume Title
- Paper No
Filter
- Title
- Author
- Author Affiliations
- Full Text
- Abstract
- Keyword
- DOI
- ISBN
- ISBN-10
- ISSN
- EISSN
- Issue
- Journal Volume Number
- References
- Conference Volume Title
- Paper No
Filter
- Title
- Author
- Author Affiliations
- Full Text
- Abstract
- Keyword
- DOI
- ISBN
- ISBN-10
- ISSN
- EISSN
- Issue
- Journal Volume Number
- References
- Conference Volume Title
- Paper No
NARROW
Format
Article Type
Subject Area
Topics
Date
Availability
1-13 of 13
Keywords: Wafer Level Packaging
Close
Follow your search
Access your saved searches in your account
Would you like to receive an alert when new items match your search?
Sort by
Journal Articles
Fumihiro Inoue, Anne Jourdain, Lan Peng, Alain Phommahaxay, Daisuke Kosemura, Ingrid De Wolf, Kenneth June Rebibis, Andy Miller, Erik Sleeckx, Eric Beyne
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. September 2018, 140(3): 031004.
Paper No: EP-17-1127
Published Online: May 11, 2018
... OURNAL OF E LECTRONIC P ACKAGING . Manuscript received December 11, 2017; final manuscript received February 14, 2018; published online May 11, 2018. Assoc. Editor: Yi-Shao Lai. 11 12 2017 14 02 2018 3D packaging Wafer level packaging Wafer scale three-dimensional...
Journal Articles
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Guest Editorial
J. Electron. Packag. June 2018, 140(2): 020301.
Paper No: EP-18-1012
Published Online: May 9, 2018
... SOC Wafer level packaging The United States Government retains, and by accepting the article for publication, the publisher acknowledges that the United States Government retains, a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this work...
Journal Articles
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Guest Editorial
J. Electron. Packag. June 2017, 139(2): 020301.
Paper No: EP-17-1032
Published Online: June 12, 2017
...Justin A. Weibel; S. Ravi Annapragada 22 03 2017 31 03 2017 3D packaging Backplanes Chip stacking Failure analysis Flexible circuits Nanotechnolgy Reliability Solder Thermal analysis Underfill Wafer level packaging ASME's International Mechanical Engineering...
Journal Articles
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. December 2016, 138(4): 041001.
Paper No: EP-14-1082
Published Online: August 10, 2016
... September 29, 2014; final manuscript received July 14, 2016; published online August 10, 2016. Assoc. Editor: Toru Ikeda. 29 09 2014 14 07 2016 3D packaging Area array COB CSP FR-4 Wafer level packaging Mechanical failures of hand-held devices lose their effective...
Journal Articles
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Review Articles
J. Electron. Packag. September 2016, 138(3): 030802.
Paper No: EP-16-1052
Published Online: July 25, 2016
..., 2016; published online July 25, 2016. Assoc. Editor: Eric Wong. 06 04 2016 22 06 2016 3D packaging High density interconnects Underfill Wafer level packaging In this paper, a flip chip is defined [ 1 – 4 ] as a chip attached to the pads of a substrate or another chip...
Journal Articles
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. December 2015, 137(4): 041005.
Paper No: EP-14-1064
Published Online: October 12, 2015
.... The most widely used methods are based on the standards set by Joint Electron Devices Engineering Council (JEDEC) [ 1 ]. Flip chip Wafer level packaging 30 06 2014 16 09 2015 Contributed by the Electronic and Photonic Packaging Division of ASME for publication in the J OURNAL...
Journal Articles
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. September 2015, 137(3): 031016.
Paper No: EP-15-1016
Published Online: July 21, 2015
...Jia Xi; Xinduo Zhai; Jun Wang; Donglun Yang; Mao Ru; Fei Xiao; Li Zhang; Chi Ming Lai FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow...
Journal Articles
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Review Articles
J. Electron. Packag. March 2015, 137(1): 010801.
Paper No: EP-14-1069
Published Online: November 14, 2014
... back to the evaporator as shown in Fig. 1 [ 1 ]. 3D packaging Flexible circuits MEMS Microsystems Nanotechnolgy Thermal analysis Wafer level packaging 04 08 2014 10 10 2014 Contributed by the Electronic and Photonic Packaging Division of ASME for publication...
Journal Articles
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Technology Review
J. Electron. Packag. June 2014, 136(2): 024002.
Paper No: EP-14-1006
Published Online: April 29, 2014
... ACKAGING . Manuscript received January 7, 2014; final manuscript received April 6, 2014; published online April 29, 2014. Assoc. Editor: Gongnan Xie. 07 01 2014 06 04 2014 Fast development of wafer level packaging (WLP) in recent years is mainly owing to the advances in integrated...
Journal Articles
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Research Papers
J. Electron. Packag. March 2010, 132(1): 011005.
Published Online: March 4, 2010
... wafer level packaging 2010 American Society of Mechanical Engineers ...
Journal Articles
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Research Papers
J. Electron. Packag. March 2008, 130(1): 011001.
Published Online: January 31, 2008
... assembling chip scale packaging creep integrated circuit manufacture printed circuits solders Taguchi methods wafer level packaging temperature cyclic loading Taguchi method lead-free solder wafer level chip scale package (WLCSP) Owing to the mismatch of coefficient of thermal...
Journal Articles
K.-F. Becker, T. Braun, A. Neumann, A. Ostmann, E. Coko, M. Koch, V. Bader, R. Aschenbrenner, H. Reichl
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Article
J. Electron. Packag. March 2005, 127(1): 1–6.
Published Online: March 21, 2005
... and laser techniques for structuring the metallization layer have been applied to generate structures for reliable interconnects capable for the use of lead-free solders. Summarized, this paper presents the process development and feasibility analysis of wafer level packaging technologies for modular SiP...
Journal Articles
Journal:
Journal of Electronic Packaging
Publisher: ASME
Article Type: Papers On Reliability
J. Electron. Packag. September 2002, 124(3): 234–239.
Published Online: July 26, 2002
...Y. T. Lin, Graduate Assistant; C. T. Peng, Graduate Assistant; K. N. Chiang, Associate Professor The demands for electronic packages with lower profile, lighter weight, and higher input/output (I/O) density have led to rapid expansion in flip chip, chip scale package (CSP) and wafer level packaging...